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DATA SHEET
MOS INTEGRATED CIRCUIT
PD720110A
USB2.0 HUB CONTROLLER
The PD720110A is an USB 2.0 hub device that comply with the Universal Serial Bus (USB) Specification Revision 2.0 and work up to 480 Mbps. USB2.0 compliant transceivers are integrated for upstream and all downstream ports. The PD720110A works backward compatible either when any one of downstream ports is connected to an USB 1.1 compliant device, or when the upstream port is connected to a USB 1.1 compliant host. Detailed function descriptions are provided in the following user's manual. Be sure to read the manual before designing.
PD720110A User's Manual: S15738E
FEATURES
* Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 1.5/12/480 Mbps) * Certified by USB implementers forum and granted with USB 2.0 high-Speed Logo * High-speed or full-speed packet protocol sequencer for Endpoint 0/1 * 4 (Max.) downstream facing ports * All downstream facing ports can handle high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction. * Supports split transaction to handle full-speed and low-speed transaction at downstream facing ports when Hub controller is working at high-speed mode. * One Transaction Translator per Hub and supports 4 non-periodic buffers * Supports self-powered mode only * Supports Over-current detection and Individual power control * Supports configurable vendor ID and product ID with external Serial ROM * Supports "non-removable" attribution on individual port * Uses 30 MHz X'tal, 30 MHz clock input, or 48 MHz clock input * Supports downstream port status with LED * HS detection indicator output * 3.3 V power supply
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
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Document No. S15737EJ5V0DS00 (5th edition) Date Published August 2004 NS CP (N) Printed in Japan
NEC Electronics Corporation 2004
PD720110A
ORDERING INFORMATION
Part Number Package 100-pin plastic LQFP (Fine pitch) (14 x 14)
PD720110AGC-8EA
BLOCK DIAGRAM
To Host/Hub downstream facing port
Upstream facing port UP_PHY
CDR
SERDES
UPC
FS_REP
SIE_2H ALL_TT F_TIM EP1 EP0 External Serial ROM ROM I/F ROM
CDR
DP(1)_PHY Downstream facing port #1 DP(2)_PHY Downstream facing port #2 DP(3)_PHY Downstream facing port #3
To Hub/Function upstream facing port To Hub/Function upstream facing port To Hub/Function upstream facing port To Hub/Function upstream facing port
DPC
APLL CLKSEL X1_CLK/X2 OSB
DP(4)_PHY Downstream facing port #4
PPB(4:1) CSB(4:1)
2
Data Sheet S15737EJ5V0DS
PD720110A
APLL ALL_TT : Generates all clocks of Hub. : Translates the high-speed transactions (split transactions) for full/low-speed device to full/low-speed transactions. ALL_TT buffers the data transfer from either upstream or downstream direction. For OUT transaction, ALL_TT buffers data from upstream port and sends it out to the downstream facing ports after speed conversion from high-speed to full/low-speed. For IN transaction, ALL_TT buffers data from downstream ports and sends it out to the upstream facing ports after speed conversion from full/low-speed to high-speed. CDR DPC DP(n)_PHY EP0 EP1 F_TIM (Frame Timer) : Data & clock recovery circuit : Downstream Port Controller handles Port Reset, Enable, Disable, Suspend and Resume : Downstream transceiver supports high-speed (480 Mbps), full-speed (12 Mbps), and low-speed (1.5 Mbps) transaction : Endpoint 0 controller : Endpoint 1 controller : Manages hub's synchronization by using micro-SOF which is received at upstream port, and generates SOF packet when full/low-speed device is attached to downstream facing port. FS_REP OSB ROM ROM I/F SERDES SIE_2H UP_PHY UPC : Full/low-speed repeater is enabled when the PD720110A is worked at full-speed mode : Oscillator Block : Contains default Descriptors : Interface block for external Serial ROM which contains user-defined Descriptors : Serializer and Deserializer : Serial Interface Engine (SIE) controls USB2.0 and 1.1 protocol sequencer : Upstream Transceiver supports high-speed (480 Mbps), full-speed (12 Mbps) transaction : Upstream Port Controller handles Suspend and Resume
Data Sheet S15737EJ5V0DS
3
PD720110A
PIN CONFIGURATION (TOP VIEW)
* 100-pin plastic LQFP (Fine pitch) (14 x 14)
PD720110AGC-8EA
100
95
90
85
80
VDD VSS X1_CLK X2 VDD PLLLOCK OSL TS1 CLKSEL TS2 TS3 TS4 TS5 TS6 SYSRSTB VSS TS7 TS8 TSO SMD TS9 TS10 SCL SDA VDD
1
76
VSS RSDPD4 DPD4 VDD DMD4 RSDMD4 VSS RSDPD3 DPD3 VDD DMD3 RSDMD3 VSS RSDPD2 DPD2 VDD DMD2 RSDMD2 VSS RSDPD1 DPD1 VDD DMD1 RSDMD1 VSS
75
5 70
10 65
15 60
20 55
25
51
VDD RPU VSS RSDPU DPU VDD DMU RSDMU VSS PC1 AVSS PC2 AVDD AVSS VSS N.C. RREF AVSS AVDD AVSS CLK30MO EPERR PORTRMV4 PORTRMV3 VDD
26
30
35
40
4
VSS PWMODE NUMPORT VBUSM PORTRMV1 PORTRMV2 CSB1 CSB2 CSB3 CSB4 VSS PPB1 PPB2 PPB3 PPB4 HSMODE AMBERBP1 GREENBP1 AMBERBP2 GREENBP2 AMBERBP3 GREENBP3 AMBERBP4 GREENBP4 VSS
Data Sheet S15737EJ5V0DS
45
50
PD720110A
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pin Name VDD VSS X1_CLK X2 VDD PLLLOCK OSL TS1 CLKSEL TS2 TS3 TS4 TS5 TS6 SYSRSTB VSS TS7 TS8 TSO SMD TS9 TS10 SCL SDA VDD Pin No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pin Name VSS PWMODE NUMPORT VBUSM PORTRMV1 PORTRMV2 CSB1 CSB2 CSB3 CSB4 VSS PPB1 PPB2 PPB3 PPB4 HSMODE AMBERBP1 GREENBP1 AMBERBP2 GREENBP2 AMBERBP3 GREENBP3 AMBERBP4 GREENBP4 VSS Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pin Name VDD PORTRMV3 PORTRMV4 EPERR CLK30MO AVSS AVDD AVSS RREF N.C. VSS AVSS AVDD PC2 AVSS PC1 VSS RSDMU DMU VDD DPU RSDPU VSS RPU VDD Pin No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Pin Name VSS RSDMD1 DMD1 VDD DPD1 RSDPD1 VSS RSDMD2 DMD2 VDD DPD2 RSDPD2 VSS RSDMD3 DMD3 VDD DPD3 RSDPD3 VSS RSDMD4 DMD4 VDD DPD4 RSDPD4 VSS
Data Sheet S15737EJ5V0DS
5
PD720110A
1. PIN INFORMATION
(1/2)
Pin Name I/O Buffer Type Active Level X1_CLK X2 SYSRSTB CLK30MO CLKSEL RPU DPD(4:1) DPU DMD(4:1) DMU RSDPD(4:1) RSDPU RSDMD(4:1) RSDMU RREF PC1 PC2 CSB(4:1) PPB(4:1) NUMPORT PWMODE VBUSM PORTRMV(2:1) PORTRMV(4:3) OSL HSMODE AMBERBP(4:1) GREENBP(4:1) SCL SDA SMD EPERR I O I O (I/O) I A B B B B O O O O A A A I (I/O) O I I I I I (I/O) O (I/O) O O O O (I/O) I/O I O (I/O) Input Output 5 V tolerant Input Output Input Analog USB high speed D+ I/O USB high speed D+ I/O USB high speed D- I/O USB high speed D- I/O USB full-speed D+ O USB full-speed D+ O USB full-speed D- O USB full-speed D- O Analog Analog Analog 5 V tolerant input 5 V tolerant N-ch open drain Input Input Input Input Input Output Output Output Output Output I/O with 5 k pull-up R Input Output High Low Low Low Low Low Low System clock input or oscillator in Oscillator out Asynchronous chip reset 30 MHz clock output Clock select signal External 1.5 k pull-up resistor control Downstream high-speed data D+ Upstream high-speed data D+ Downstream high-speed data D- Upstream high-speed data D- Downstream full-speed data D+ and RS resistor terminal Upstream full-speed data D+ and RS resistor terminal Downstream full-speed data D- and RS resistor terminal Upstream full-speed data D- and RS resistor terminal Reference resistor Capacitor for PLL Capacitor for PLL Port's overcurrent status input Port's power supply control output Number of available ports Power mode select VBus monitor Removable/Non-removable select Removable/Non-removable select Indication for suspend state Indication for high-speed operation Indication for downstream port status with amber colored LED Indication for downstream port status with green colored LED Serial ROM clock out Serial ROM data Serial ROM input enable Indication for serial ROM error Function
6
Data Sheet S15737EJ5V0DS
PD720110A
(2/2)
Pin Name I/O Buffer Type Active Level PLLLOCK TS(1) TS(10:2) TSO VDD AVDD VSS AVSS N.C. O (I/O) I I I/O Output Input with 12 k pull-down R Input I/O Indication when PLL is locked Test signal Test signal Test signal VDD VDD for analog circuit VSS VSS for analog circuit Not connected Function
Remarks 1. "5 V tolerant" means that the buffer is 3 V buffer with 5 V tolerant circuit. 2. The signal marked as "(I/O)" in the above table operates as I/O signals during testing. However, they do not need to be considered in normal use.
Data Sheet S15737EJ5V0DS
7
PD720110A
2.
2.1 * * * * * * * * *
ELECTRICAL SPECIFICATIONS
Buffer List 5 V schmitt buffer SYSRSTB, CSB(4:1) 3.3 V oscillator block X1_CLK, X2 3.3 V input buffer CLKSEL, TS(10:1), SMD, PWMODE, NUMPORT, VBUSM, PORTRMV(4:1) 3.3 V IOL = 6 mA output buffer PLLLOCK, OSL, TSO, SCL, CLK30MO 3.3 V IOL = 12 mA output buffer EPERR 3.3 V IOL = 6 mA schmitt I/O buffer with 5 k pull-up resistor SDA 5 V IOL = 12 mA output buffer HSMODE, AMBERBP(4:1), GREENBP(4:1) 5 V IOL = 12 mA N-ch open drain buffer PPB(4:1) USB2.0 interface RPU, DPU, DMU, RSDPU, RSDMU, DPD(4:1), DMD(4:1), RSDPD(4:1), RSDMD(4:1), RREF, PC1, PC2 Above, "5 V" refers to a 3 V buffer that is 5 V tolerant (has 5 V maximum voltage). Therefore, it is possible to have
a 5 V connection for an external bus, but the output level will be only up to 3 V, which is the VDD voltage.
8
Data Sheet S15737EJ5V0DS
PD720110A
2.2 Terminology
Terms Used in Absolute Maximum Ratings
Parameter Power supply voltage Input voltage Output voltage Output current Operating temperature Storage temperature Symbol VDD VI VO IO TA Tstg Meaning Indicates voltage range within which damage or reduced reliability will not result when power is applied to a VDD pin. Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin. Indicates voltage range within which damage or reduced reliability will not result when power is applied to an output pin. Indicates absolute tolerance values for DC current to prevent damage or reduced reliability when a current flow out of or into an output pin. Indicates the ambient temperature range for normal logic operations. Indicates the element temperature range within which damage or reduced reliability will not result while no voltage or current are applied to the device.
Terms Used in Recommended Operating Range
Parameter Power supply voltage High-level input voltage Symbol VDD VIH Meaning Indicates the voltage range for normal logic operations occur when VSS = 0V. Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the high level states for normal operation of the input buffer. * If a voltage that is equal to or greater than the "MIN." value is applied, the input voltage is guaranteed as high level voltage. Low-level input voltage VIL Indicates the voltage, which is applied to the input pins of the device, is the voltage indicates that the low level states for normal operation of the input buffer. * If a voltage that is equal to or lesser than the "MAX." value is applied, the input voltage is guaranteed as low level voltage. Hysteresis voltage VH Indicates the differential between the positive trigger voltage and the negative trigger voltage.
Terms Used in DC Characteristics
Parameter Off-state output leakage current Output short circuit current Low-level output current High-level output current Symbol IOZ IOS IOL IOH Meaning Indicates the current that flows from the power supply pins when the rated power supply voltage is applied when a 3-state output has high impedance. Indicates the current that flows when the output pin is shorted (to GND pins) when output is at high-level. Indicates the current that flows to the output pins when the rated low-level output voltage is being applied. Indicates the current that flows from the output pins when the rated highlevel output voltage is being applied.
Data Sheet S15737EJ5V0DS
9
PD720110A
2.3 Electrical Specifications
Absolute Maximum Ratings
Parameter Power supply voltage Input voltage 3.3 V input voltage 5 V input voltage Output voltage 3.3 V output voltage 5 V output voltage Operating temperature Storage temperature TA Tstg VO VO < VDD + 0.5 V VO < VDD + 3.0 V -0.5 to +4.6 -0.5 to +6.6 0 to +70 -65 to +150 V V C C Symbol VDD VI VI < VDD + 0.5 V VI < VDD + 3.0 V -0.5 to +4.6 -0.5 to +6.6 V V Condition Rating -0.5 to +4.6 Unit V
Caution Product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameters. That is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. The ratings and conditions indicated for DC characteristics and AC characteristics represent the quality assurance range during normal operation. Recommended Operating Ranges
Parameter Operating voltage High-level input voltage 3.3 V High-level input voltage 5.0 V High-level input voltage Low-level input voltage 3.3 V Low-level input voltage 5.0 V Low-level input voltage Hysteresis voltage Input rise time for SYSRSTB Reset time
Note
Symbol VDD VIH
Condition
MIN. 3.14
TYP. 3.30
MAX. 3.46
Unit V
2.0 2.0 VIL 0 0 VH tr tRST 0.005 0.3
VDD 5.5
V V
0.8 0.8 1.5 10 90
V V V ms ms
Note Drive Low on SYSRSTB pin when only in Power On Reset timing.
10
Data Sheet S15737EJ5V0DS
PD720110A
Figure 2-1. Power On Reset Timing
VDD VDD(MIN) 2.7 V
VDD
RST
0.3 V VSS tRST Power supply ON tr
DC Characteristics
Parameter Off-state output leakage current Output short circuit current Low-level output current 3.3 V low-level output current 3.3 V low-level output current 5.0 V low-level output current High-level output current 3.3 V high-level output current 3.3 V high-level output current 5.0 V high-level output current IOH VOH = 2.4 V VOH = 2.4 V VOH = 2.4 V -6 -12 -2 mA mA mA Symbol IOZ IOS IOL VOL = 0.4 V VOL = 0.4 V VOL = 0.4 V 6 12 12 mA mA mA
Note
Condition VO = VDD or GND
MIN.
MAX. 10 -250
Unit
A
mA
Note The output short circuit time is one second or less and is only for one pin on the LSI.
Data Sheet S15737EJ5V0DS
11
PD720110A
USB Interface Block
Parameter Serial Resistor between DPx (DMx) and RSDPx (RSDMx). Output pin impedance Bus pull-up resistor on upstream facing port Bus pull-up resistor on downstream facing port Termination voltage for upstream facing port pullup (full-speed) Input Levels for Low-/full-speed: High-level input voltage (drive) High-level input voltage (floating) Low-level input voltage Differential input sensitivity Differential common mode range Output Levels for Low-/full-speed: High-level output voltage Low-level output voltage SE1 Output signal crossover point voltage Input Levels for High-speed: High-speed squelch detection threshold (differential signal) High-speed disconnect detection threshold (differential signal) High-speed data signaling common mode voltage range High-speed differential input signaling level Output Levels for High-speed: High-speed idle state High-speed data signaling high High-speed data signaling low Chirp J level (different signal) Chirp K level (different signal) VHSOI VHSOH VHSOL VCHIRPJ VCHIRPK -10.0 360 -10.0 700 -900 +10 440 +10 1100 -500 mV mV mV mV mV VHSSQ VHSDSC VHSCM See Figure 2-5. 100 525 -50 150 625 +500 mV mV mV VOH VOL VOSE1 VCRS RL of 14.25 k to GND RL of 1.425 k to 3.6 V 2.8 0.0 0.8 1.3 2.0 3.6 0.3 V V V V VIH VIHZ VIL VDI VCM (D+) - (D-) Includes VDI range 0.2 0.8 2.5 2.0 2.7 3.6 0.8 V V V V V ZHSDRV RPU RPD VTERM Includes RS resistor 40.5 1.425 14.25 3.0 49.5 1.575 15.75 3.6 k k V Symbol RS Conditions MIN 35.64 MAX 36.36 Unit
12
Data Sheet S15737EJ5V0DS
PD720110A
Figure 2-2. Differential Input Sensitivity Range for Low-/full-speed
Differential Input Voltage Range Differential Output Crossover Voltage Range
-1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 4.6
Input Voltage Range (Volts)
Figure 2-3. Full-speed Buffer VOH/IOH Characteristics for High-speed Capable Transceiver
VDD-3.3
VDD-2.8
VDD-2.3
VDD-1.8
VDD-1.3
VDD-0.8
VDD-0.3 VDD 0
-20
Iout (mA)
-40 Min. -60 Max. -80 Vout (V)
Figure 2-4. Full-speed Buffer VOL/IOL Characteristics for High-speed Capable Transceiver
80 Max. 60 Min. 40
Iout (mA)
20
0 0 0.5 1 1.5 Vout (V) 2 2.5 3
Data Sheet S15737EJ5V0DS
13
PD720110A
Figure 2-5. Receiver Sensitivity for Transceiver at DP/DM
Level 1
+400 mV Differential
Point 3
Point 4
Point 1
Point 2
0V Differential
Point 5
Point 6
Level 2
-400 mV Differential
0%
Unit Interval
100%
Figure 2-6. Receiver Measurement Fixtures
Test Supply Voltage 15.8 USB Connector Nearest Device Vbus D+ DGnd 50 Coax 50 Coax + To 50 Inputs of a High Speed Differential Oscilloscope, or 50 Outputs of a High Speed Differential Data Generator -
15.8
143
143
14
Data Sheet S15737EJ5V0DS
PD720110A
Power Consumption
Parameter Power Consumption Symbol PW-0 Condition The power consumption under the state without suspend. All the ports does not connect to any function.
Note 1
TYP.
Unit
Hub controller is operating at full-speed mode. Hub controller is operating at high-speed mode. PW-2 The power consumption under the state without suspend. The number of active ports is 2.
Note 2
185 270
mA mA
Hub controller is operating at full-speed mode. Hub controller is operating at high-speed mode. PW-3 The power consumption under the state without suspend. The number of active ports is 3.
Note 2
190 400
mA mA
Hub controller is operating at full-speed mode. Hub controller is operating at high-speed mode. PW-4 The power consumption under the state without suspend. The Note 2 number of active ports is 4. Hub controller is operating at full-speed mode. Hub controller is operating at high-speed mode. PW_S The power consumption under suspend state. The internal clock is stopped.
193 460
mA mA
196 525 1.3
mA mA mA
Notes
1. When any device is not connected to all the ports of HC, the power consumption for HC does not depend on the number of active ports. 2. The number of active ports is set by the value of Port No field in PCI configuration space EXT register.
System Clock Ratings
Parameter Clock frequency Symbol fCLK X'tal Oscillator block Clock Duty cycle tDUTY Condition MIN. -500 ppm -500 ppm 40 48 50 TYP. 30 MAX. +500 ppm +500 ppm 60 MHz % Unit MHz
Remarks 1. Recommended accuracy of clock frequency is 100 ppm. 2. Required accuracy of X'tal or oscillator block is including initial frequency accuracy, the spread of X'tal capacitor loading, supply voltage, temperature, and aging, etc.
Data Sheet S15737EJ5V0DS
15
PD720110A
AC Characteristics (VDD = 3.14 to 3.46 V, TA = 0 to +70C) USB Interface Block (1/4)
Parameter Low-speed Electrical Characteristics Rise time (10% to 90%) Fall time (90% to 10%) Differential rise and fall time matching Low-speed data rate Hub differential data delay (Figure 2-9) Hub differential driver jitter (including cable) (Figure 2-9): Downstream facing port To next transition For paired transitions Upstream facing port To next transition For paired transitions Data bit width distortion after SE0 (Figure 2-9) Hub EOP delay relative to THDD (Figure 2-10) Hub EOP output width skew (Figure 2-10) Full-speed Electrical Characteristics Rise time (10% to 90%) Fall time (90% to 10%) Differential rise and fall time matching Full-speed data rate Frame interval Consecutive frame interval jitter Source jitter total (including frequency tolerance) (Figure 2-11): To next transition For paired transitions Source jitter for differential transition to SE0 transition (Figure 2-12) tDJ1 tDJ2 tFDEOP -3.5 -4.0 -2 +3.5 +4.0 +5 ns ns ns tFR tFF tFRFM tFDRATHS tFRAME tRFI No clock adjustment Note CL = 50 pF, RS = 36 CL = 50 pF, RS = 36 (tFR/tFF) Average bit rate 90 11.9940 0.9995 111.11 12.0060 1.0005 42 % Mbps ms ns 4 20 ns 4 20 ns tLHESK -300 +300 ns tLEOPD 0 200 ns tLUHJ1 tLUHJ2 tLSOP -45 -15 -60 +45 +15 +60 ns ns ns tLDHJ1 tLDHJ2 -45 -45 +45 +45 ns ns tLR tLF tLRFM tLDRATHS tLHDD CL = 50 pF to 150 pF, RS = 36 CL = 50 pF to 150 pF, RS = 36 (tLR/tLF) Note Average bit rate 75 75 80 1.49925 300 300 125 1.50075 300 ns ns % Mbps ns Symbol Conditions MIN. MAX. Unit
Note Excluding the first transition from the Idle state.
16
Data Sheet S15737EJ5V0DS
PD720110A
(2/4)
Parameter Symbol Conditions MIN. MAX. Unit
Full-speed Electrical Characteristics (Continued) Receiver jitter (Figure 2-13): To Next Transition For Paired Transitions Source SE0 interval of EOP (Figure 2-12) Receiver SE0 interval of EOP (Figure 2-12) Width of SE0 interval during differential transition Hub differential data delay (with cable) Hub differential data delay (without cable) (Figure 2-9) Hub differential driver jitter (including cable) (Figure 2-9): To next transition For paired transitions Data bit width distortion after SE0 Figure 2-9) Hub EOP delay relative to THDD (Figure 2-10) Hub EOP output width skew (Figure 2-10) High-speed Electrical Characteristics Rise time (10% to 90%) Fall time (90% to 10%) Driver waveform High-speed data rate Microframe interval Consecutive microframe interval difference Data source jitter Receiver jitter tolerance Hub data delay (without cable) Hub data jitter Hub delay variation range Hub Event Timings Time to detect a downstream facing port connect event (Figure 2-15): Awake hub Suspended hub Time to detect a disconnect event at a hub's downstream facing port (Figure 2-14) tDDIS 2.5 2.5 2.0 2000 12000 2.5 tDCNN tHSR tHSF See Figure 2-7. tHSDRAT tHSFRAM tHSRFI See Figure 2-7. See Figure 2-5. tHSHDD See Figure 2-5, Figure 2-7. tHSHDV 5 highspeed Bit times 36 highspeed+4 ns Bit times 479.760 124.9375 480.240 125.0625 4 highspeed Mbps 500 500 ps ps tHDJ1 tHDJ2 tFSOP tFEOPD tFHESK -3 -1 -5 0 -15 +3 +1 +5 15 +15 ns ns ns ns ns tJR1 tJR2 tFEOPT tFEOPR tFST tHDD1 tHDD2 -18.5 -9 160 82 14 70 44 +18.5 +9 175 ns ns ns ns ns ns ns
s
Bit times
s s s
Data Sheet S15737EJ5V0DS
17
PD720110A
(3/4)
Parameter Hub Event Timings (Continued) Duration of driving resume to a downstream port (only from a controlling hub) Time from detecting downstream resume to rebroadcast Duration of driving reset to a downstream facing port (Figure 2-16) Time to detect a long K from upstream Time to detect a long SE0 from upstream Duration of repeating SE0 upstream (for low-/full-speed repeater) Inter-packet delay (for high-speed) of packets traveling in same direction Inter-packet delay (for high-speed) of packets traveling in opposite direction Inter-packet delay for device/root hub response with detachable cable for highspeed Time of which a Chirp J or Chirp K must be continuously detected (filtered) by hub or device during Reset handshake Time after end of device Chirp K by which hub must start driving first Chirp K in the hub's chirp sequence Time for which each individual Chirp J or Chirp K in the chirp sequence is driven downstream by hub during reset Time before end of reset by which a hub must end its downstream chirp sequence Time from internal power good to device pulling D+ beyond VIHZ (Figure 2-16) Debounce interval provided by USB system software after attach (Figure 2-16) Maximum duration of suspend averaging interval Period of idle bus before device can initiate resume Duration of driving resume upstream Resume recovery time Time to detect a reset from upstream for non high-speed capable devices Reset recovery time (Figure 2-16) tDCHSE0 tSIGATT tATTDB tSUSAVGI tWTRSM tDRSMUP tRSMRCY tDETRST tRSTRCY Remote-wakeup is enabled 5 1 10 2.5 10000 10 15 100 500 100 100 1 tDCHBIT 40 60 tWTDCH 100 tFILT 2.5 tURSM tDRST tURLK tURLSE0 tURPSE0 tHSIPDSD tHSIPDOD tHSRSPIPD1 88 8 192 Only for a SetPortFeature (PORT_RESET) request 10 2.5 2.5 1.0 20 100 10000 23 ms ms tDRSMDN 20 ms Symbol Conditions MIN. MAX. Unit
s s
FS Bit times Bit times Bit times Bit times
s
s
s
s
ms ms s ms ms ms
s
ms
18
Data Sheet S15737EJ5V0DS
PD720110A
(4/4)
Parameter Hub Event Timings (Continued) Inter-packet delay for full-speed Inter-packet delay for device response with detachable cable for full-speed SetAddress() completion time Time to complete standard request with no data Time to deliver first and subsequent (except last) data for standard request Time to deliver last data for standard request Time for which a suspended hub will see a continuous SE0 on upstream before beginning the high-speed detection handshake Time a hub operating in non-suspended full-speed will wait after start of SE0 on upstream before beginning the high-speed detection handshake Time a hub operating in high-speed will wait after start of SE0 on upstream before reverting to full-speed Time a hub will wait after reverting to fullspeed before sampling the bus state on upstream and beginning the high-speed will wait after start of SE0 on upstream before reverting to full-speed Minimum duration of a Chirp K on upstream from a hub within the reset protocol Time after start of SE0 on upstream by which a hub will complete its Chirp K within the reset protocol Time between detection of downstream chip and entering high-speed state Time after end of upstream Chirp at which hub reverts to full-speed default state if no downstream Chirp is detected tWTHS tWTFS 1.0 500 2.5 tUCHEND 7.0 ms tUCH 1.0 ms tWTRSTHS 100 875 ms tWTREV 3.0 3.125 ms tWTRSTFS 2.5 3000 ms tIPD tRSPIPD1 tDSETADDR tDRQCMPLTND tDRETDATA1 tDRETDATAN tFILTSE0 2.5 2 6.5 50 50 500 50 Bit times Bit times ms ms ms ms Symbol Conditions MIN. MAX. Unit
s
s
ms
Data Sheet S15737EJ5V0DS
19
PD720110A
Clock & Overcurrent Response Timing
Parameter CLK30MO cycle time CLK30MO high level width CLK30MO low level width Overcurrent response time from CSB low to PPB high (Figure 2-19) Symbol tC3C tC3H tC3L tOC 15.9 15.9 500 Condition MIN. TYP. 33.33 17.5 17.5 625 MAX. Unit ns ns ns
s
Figure 2-7. Transmit Waveform for Transceiver at DP/DM
Level 1
+400 mV Differential
Point 3 Point 4
Point 1
Point 2
0V Differential
Point 5 Level 2
Point 6
-400 mV Differential
Unit Interval 0% 100%
Figure 2-8. Transmitter Measurement Fixtures
Test Supply Voltage 15.8 USB Connector Nearest Device Vbus D+ DGnd 50 Coax 50 Coax + To 50 Inputs of a High Speed Differential Oscilloscope, or 50 Outputs of a High Speed Differential Data Generator -
15.8
143
143
20
Data Sheet S15737EJ5V0DS
PD720110A
Timing Diagram Figure 2-9. Hub Differential Delay, Differential Jitter, and SOP Distortion
Upstream End of Cable VSS
50% Point of Initial Swing
Upstream Port of Hub VSS
Crossover Point
Downstream Port of Hub VSS
Hub Delay Downstream tHDD1
Downstream Port of Hub VSS
Hub Delay Downstream tHDD2
50% Point of Initial Swing
A. Downstream Hub Delay with Cable
B. Downstream Hub Delay without Cable
Downstream Port of Hub VSS Upstream Port or End of Cable VSS
Crossover Point
Hub Delay Upstream tHDD1 tHDD2
Crossover Point
C. Upstream Hub Delay with or without Cable
Upstream end of cable
Upstream port
Downstream port Plug
Receptacle
Host or Hub
Hub
Function
Downstream signaling Upstream signaling
Hub Differential Jitter: tHDJ1 = tHDDx(J) - tHDDx(K) or tHDDx(K) - tHDDx(J) Consecutive Transitions tHDJ2 = tHDDx(J) - tHDDx(J) or tHDDx(K) - tHDDx(K) Paired Transitions Bit after SOP Width Distortion (same as data jitter for SOP and next J transition): tFSOP = tHDDx(next J) - tHDDx(SOP) Low-speed timings are determined in the same way for: tLHDD, tLDHJ1, tLDJH2, tLUHJ1, tLUJH2, and tLSOP
Data Sheet S15737EJ5V0DS
21
PD720110A
Figure 2-10. Hub EOP Delay and EOP Skew
Upstream End of Cable VSS
50% Point of Initial Swing Upstream Port of Hub VSS tEOP- tEOP+ tEOP- tEOP+ Downstream Port of Hub VSS Crossover Point Extended
Downstream Port of Hub VSS A. Downstream EOP Delay with Cable
B. Downstream EOP Delay without Cable
Downstream Port of Hub VSS tEOPUpstream Port or End of Cable VSS
Crossover Point Extended
tEOP+ Crossover Point Extended
C. Upstream EOP Delay with or without Cable
EOP Delay: tFEOPD = tEOPy - tHDDx (tEOPy means that this equation applies to tEOP- and tEOP+) EOP Skew: tFHESK = tEOP+ - tEOPLow-speed timings are determined in the same way for: tLEOPD and tLHESK
22
Data Sheet S15737EJ5V0DS
PD720110A
Figure 2-11. USB Differential Data Jitter for Full-speed
tPERIOD Differential Data Lines
Crossover Points
Consecutive Transitions N x tPERIOD + tDJ1 Paired Transitions N x tPERIOD + tDJ2
Figure 2-12. USB Differential-to-EOP Transition Skew and EOP Width for Full-speed
tPERIOD Differential Data Lines
Crossover Point
Crossover Point Extended
Diff. Data-toSE0 Skew N x tPERIOD + tFDEOP, tLDEOP
Source EOP Width: tFEOPT tLEOPT Receiver EOP Width: tFEOPR tLEOPR
Figure 2-13. USB Receiver Jitter Tolerance for Full-speed
tPERIOD Differential Data Lines
tJR tJR1 tJR2
Consecutive Transitions N x tPERIOD + tJR1 Paired Transitions N x tPERIOD + tJR2
Data Sheet S15737EJ5V0DS
23
PD720110A
Figure 2-14. Low-/full-speed Disconnect Detection
D+/DVIHZ (min)
VIL D-/D+ VSS tDDIS Device Disconnected Disconnect Detected
Figure 2-15. Full-/high-speed Device Connect Detection
D+ VIH
DVSS tDCNN Device Connected Connect Detected
Figure 2-16. Power-on and Connection Events Timing
Hub port power OK Hub port power-on
Attach Detected
Reset Recovery Time
4.01 V
VBUS VIH (min) VIH D+ or D-
t2SUSP
tDRST
USB System Software reads device speed
tSIGATT t1 tATTDB tRSTRCY
24
Data Sheet S15737EJ5V0DS
PD720110A
Figure 2-17. Clock Output
tC3C
CLKO30MO
tC3H
Figure 2-18. CSB/PPB Timing
500 s 500 s
tC3L
500 s
500 s
Hub power supply BUS reset Up port D+ line
PPB pin output
Output cut-off
CSB pin input Port power supply ON CSB pin operation region
DEVICE connection inrush current
Overcurrent generation
Power supply ON Bus power: Up port connection Self-power: Power supply ON
CSB detection delay time
CSB active period
Note The active period of the CSB pin is in effect only when the PPB pin is ON. There is a delay time of approximately 500 s duration at the CSB pin. Figure 2-19. Overcurrent Response Timing
VDD CSB(4:1) VSS tOC VDD PPB(4:1) VSS
Data Sheet S15737EJ5V0DS
25
PD720110A
3. PACKAGE DRAWING
100-PIN PLASTIC LQFP (FINE PITCH) (14x14)
A B
75 76
51 50
detail of lead end S CD Q R
100 1
26 25
F G P
H
I
M
J K
S
N S
L M
NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition.
ITEM A B
C
MILLIMETERS 16.000.20 14.000.20
14.000.20
D
F
16.000.20
1.00
G
H
1.00
0.22 +0.05 -0.04
I J
0.08 0.50 (T.P.) 1.000.20
0.500.20
0.17 +0.03 -0.07
K
L
M
N P Q
R
0.08 1.400.05 0.100.05
3 +7 -3
S
1.60 MAX.
S100GC-50-8EU, 8EA-2
26
Data Sheet S15737EJ5V0DS
PD720110A
4. RECOMMENDED SOLDERING CONDITIONS
The PD720110A should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html)
PD720100AGC-8EA:
Soldering Method Infrared reflow
100-pin plastic LQFP (Fine pitch) (14 x 14)
Soldering Conditions Package peak temperature: 235C, Time: 30 seconds max. (at 210C or higher), Count: Three times or less Exposure limit: 2 days
Note
Symbol IR35-102-3
(after that, prebake at 125C for 10 hours) -
Partial heating
Pin temperature: 300C max., Time: 3 seconds max. (per pin row)
Note After opening the dry pack, store it at 25C or less and 65% RH or less for the allowable storage period.
Data Sheet S15737EJ5V0DS
27
PD720110A
[MEMO]
28
Data Sheet S15737EJ5V0DS
PD720110A
[MEMO]
Data Sheet S15737EJ5V0DS
29
PD720110A
[MEMO]
30
Data Sheet S15737EJ5V0DS
PD720110A
NOTES FOR CMOS DEVICES
1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN). 2 HANDLING OF UNUSED INPUT PINS Unconnected CMOS device inputs can be cause of malfunction. If an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND via a resistor if there is a possibility that it will be an output pin. All handling related to unused pins must be judged separately for each device and according to related specifications governing the device. 3 PRECAUTION AGAINST ESD A strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. Environmental control must be adequate. When it is dry, a humidifier should be used. It is recommended to avoid using insulators that easily build up static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work benches and floors should be grounded. The operator should be grounded using a wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with mounted semiconductor devices. 4 STATUS BEFORE INITIALIZATION Power-on does not necessarily define the initial status of a MOS device. Immediately after the power source is turned ON, devices with reset functions have not yet been initialized. Hence, power-on does not guarantee output pin levels, I/O settings or contents of registers. A device is not initialized until the reset signal is received. A reset operation must be executed immediately after power-on for devices with reset functions. 5 POWER ON/OFF SEQUENCE In the case of a device that uses different power supplies for the internal operation and external interface, as a rule, switch on the external power supply after switching on the internal power supply. When switching the power supply off, as a rule, switch off the external power supply and then the internal power supply. Use of the reverse power on/off sequences may result in the application of an overvoltage to the internal elements of the device, causing malfunction and degradation of internal elements due to the passage of an abnormal current. The correct power on/off sequence must be judged separately for each device and according to related specifications governing the device. 6 INPUT OF SIGNAL DURING POWER OFF STATE Do not input signals or an I/O pull-up power supply while the device is not powered. The current injection that results from input of such a signal or I/O pull-up power supply may cause malfunction and the abnormal current that passes in the device at this time may cause degradation of internal elements. Input of signals during the power off state must be judged separately for each device and according to related specifications governing the device.
Data Sheet S15737EJ5V0DS
31
PD720110A
USB logo is a trademark of USB Implementers Forum, Inc.
* The information in this document is current as of August, 2004. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. NEC Electronics assumes no responsibility for any errors that may appear in this document. * NEC Electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC Electronics products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Electronics or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. NEC Electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While NEC Electronics endeavors to enhance the quality, reliability and safety of NEC Electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC Electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. * NEC Electronics products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to NEC Electronics products developed based on a customerdesignated "quality assurance program" for a specific application. The recommended applications of an NEC Electronics product depend on its quality grade, as indicated below. Customers must check the quality grade of each NEC Electronics product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC Electronics products is "Standard" unless otherwise expressly specified in NEC Electronics data sheets or data books, etc. If customers wish to use NEC Electronics products in applications not intended by NEC Electronics, they must contact an NEC Electronics sales representative in advance to determine NEC Electronics' willingness to support a given application. (Note) (1) "NEC Electronics" as used in this statement means NEC Electronics Corporation and also includes its majority-owned subsidiaries. (2) "NEC Electronics products" means any product developed or manufactured by or for NEC Electronics (as defined above).
M8E 02. 11-1

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